Wei Hong

Southeast University, China

Wei Hong received the B.S. degree from the University of Information Engineering, Zhengzhou, China, in 1982, and the M.S. and PhD degrees from Southeast University, Nanjing, China, in 1985 and 1988, respectively, all in radio engineering.

He is currently a professor of the School of Information Science and Engineering, Southeast University. In 1993, 1995, 1996, 1997 and 1998, he was a short-term visiting scholar with the University of California at Berkeley and at Santa Cruz, respectively. He has been engaged in numerical methods for electromagnetic problems, millimeter wave and terahertz theory and technology, antennas, RF technology for wireless communications etc. He has authored and co-authored over 400 technical publications and 5 books. He twice awarded the National Natural Prizes of China, once awarded the National Science and Technology Progress Award, four times awarded the first-class Science and Technology Progress Prizes issued by the Ministry of Education of China and Jiangsu Province Government, and 2021 IEEE MTT-S Microwave Prize etc.

Dr. Hong is a Fellow of IEEE, Fellow of CIE, the vice presidents of the CIE Microwave Society and Antenna Society, and was an elected IEEE MTT-S AdCom Member during 2014-2016, served as the Associate Editor of the IEEE Trans. on MTT from 2007 to 2010.

Speech Title: Research Progress in Terahertz Devices, Chips, and Systems

Abstract: In this talk, the recent research progress in terahertz (THz) devices, chips and systems in the State Key Laboratory of Millimeter Waves (SKLMMW) of Southeast University and cooperative enterprises are reviewed. 

Tianchun Ye

University of Chinese Academy of Sciences, China

Tianchun Ye, born in 1965, he is an IEEE Fellow and a graduate of the Department of Electronic Engineering at Fudan University. He previously served as the Director of the Institute of Microelectronics, Chinese Academy of Sciences, and led a National Science and Technology Major Project. He has received three National Technology Invention Awards and four First-Class Invention Awards at the ministerial and provincial levels. Leading his team in over a decade of persistent research, he proposed a series of innovative technical methodologies and achieved multiple major inventions at the forefront of international standards. These technologies have been adopted by leading enterprises both in China and abroad for the mass production of cutting-edge products, making pioneering contributions to the self-reliance and development of China's advanced integrated circuit processes.

Speech Title: Technology Innovation in Integrated Circuit Transistor Process

Abstract: Integrated circuit process evolution is the fundamental basis for the development of modern information and artificial intelligence technologies. Over the past few decades, China has been making continuous efforts in this field. Starting from the 90nm node, integrated circuit CMOS transistors have demanded the development of new processes, materials, and structures to overcome key bottlenecks in PPA scaling by generations. The Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) has long been engaged in the research and development of innovative transistor technologies. They have made a great breakthrough on technical challenges such as precise gate control, transistor performance modulation, and structural scaling in both 22nm high-k/metal gate-last, 14nm FinFET, and up-to-date GAA transistor processes, established a technical system with comprehensive independent intellectual property rights, and successfully applied it to domestic and international cutting-edge integrated circuit products.

Tian-ling Ren

Tsinghua University, China

Prof. Tian-Ling Ren is a distinguished professor at Tsinghua University. He serves as Vice Dean of the School of Information Science and Technology, and Director of the Tsinghua University-BEIGC Joint Research Center. He is IEEE Fellow, and Chinese Society of Micro-Nano Technology Fellow.

His research focuses on intelligent micro-nano electronic devices, 2D nanoelectronic devices, flexible wearable systems, and intelligent sensing chips. He has led many national key research projects and achieved world-renowned innovations, including the world’s shortest gate-length transistor, the first graphene intelligent artificial throat, high-performance flexible AI chips, and intelligent healthcare systems.

He has published over 900 papers in top journals and conferences, such as Nature and IEDM, with more than 30,000 Google Scholar citations. He holds more than 200 patents and has been selected as an Elsevier Highly Cited Researcher for consecutive years.

Speech Title: Novel Device and Chip Technologies Driving Moore’s Law

Abstract: As Moore’s Law faces severe physical bottlenecks—including thermal and quantum mechanical limits—sustaining the exponential growth of integrated circuits requires innovations beyond simple dimensional scaling. This talk presents recent advances in novel device and chip technologies that both extend and go beyond Moore’s Law. In the extending direction, we demonstrate a sub-1nm gate-length transistor with a physical gate length of only 0.34 nm using a graphene edge gate and a MoS₂ channel, pushing device scaling to the atomic limit. We also introduce flexible inmemory computing chips that achieve high clock frequency and energy efficiency, enabling edge computing on conformable substrates. In the beyondMoore direction, we highlight smart graphenebased artificial throats that restore voice communication for laryngectomees, and a motionartifactfree 12lead dynamic ECG system with onchip AI processing for unobtrusive, continuous cardiac monitoring. These developments illustrate that novel devices enabled by lowdimensional materials and flexible electronics can effectively promote Moore’s Law with wide intelligent healthcare and humanmachine interface applications.

Pui-In Mak

University of Macau, China

Pui-In Mak is Chair Professor at the University of Macau, Macau, China, Director of the State-Key Laboratory of Analog and Mixed-Signal VLSI, and Director of the Guangdong-Macao Joint Laboratory for Modular Chip Design and Testing. His research interests are on analog and radio-frequency circuits and systems for wireless and multidisciplinary innovations. He received the Xplorer Prize in 2022, and is recognized as one of the Top Contributing Authors of ISSCC at its 70th anniversary in 2023, and the Medal of Merit-Education from the Macau government in 2024. He is currently AdCom Member of the IEEE Solid-State Circuits Society and Editor-in-Chief of the IEEE Solid-State Circuits Letters, and was an Associate Editor of the IEEE Journal of Solid-State Circuits. He is a Changjiang Scholar, Overseas Expert of the Chinese Academy of Sciences, Fellow of the IEEE, IET and UK Royal Society of Chemistry. He is a foreign academician of the Academy of Sciences of Lisbon (ACL), Portugal.

Speech Title: The Frontiers of Microelectronic Engineering over the Next Decade

Abstract: This talk explores the transformative landscape of microelectronic engineering over the next decade. As we navigate advancements in integrated circuits (IC) with artificial intelligence (AI), we will highlight emerging trends that promise to redefine the experience of humans interact with their surroundings that will be collectively proactive, and highly personalized. Key topics will include the embodiment of power-efficient edge AI chips in wearables/robots, ultra-low-power radio chips for battery-free wireless connectivity, and easy-to-use advanced instruments, shifting towards a highly-efficient healthcare home system. By examining the current challenges and opportunities of IC+AI, this presentation aims to envision a future where microelectronics plays a pivotal role in re-shaping our quality of life. Join us as we delve into the frontiers that will surf on the next big wave of engineering breakthroughs.

Mansun Chan

The Hong Kong University of Science and Technology, China

Dr. Mansun Chan is the Alex Wong Siu Wah Gigi Wong Fook Chi Professor of Engineering and Chair Professor in the Department of Electronic and Computer Engineering at the Hong Kong University of Science and Technology. He received his Ph.D. degree from the University of California, Berkeley. As an internationally recognized leader in semiconductor devices and compact modeling, he has authored over 350 journal papers and 500 conference papers. He is best known for his pivotal contributions to the unified BSIM compact model for SPICE, which became the first widely adopted industrial standard MOSFET model, and for leading the first demonstration of stacked CFET technology to extend CMOS scaling beyond the 2‑nm node.

Beyond research, Prof. Chan has played a major role in technology leadership and professional education. He is an IEEE Fellow and Distinguished Lecturer, has served in multiple leadership roles within the IEEE Electron Device Society, and has been deeply involved in advancing engineering education through large‑scale online courses, outreach programs, and industry engagement. He is also active in entrepreneurship, having co‑founded and invested in numerous technology startups.

Speech Title: The Role of Compact Modeling in Bridging Conceptual Understanding and Production in CMOS Technology

Abstract: This talk reviews the historical role of compact modeling in enabling CMOS technology from academic research to industrial production. It begins with the development of SPICE as an academic circuit simulator and the early Meyer model, which supported initial MOS circuit analysis. As CMOS scaled, compact models evolved toward standardization, with BSIM3 becoming the first widely adopted industrial standard. The talk contrasts academic and industrial modeling requirements and shows how compact models actively guided technology development and manufacturing. Finally, it discusses the continuing importance of parameter extraction and physics‑based modeling methodologies in the emerging AI‑driven modeling era.

Cher Ming Tan

Chang Gung University, Taiwan

Professor Cher Ming Tan is a leading authority in reliability engineering, currently serving as a Professor at Chang Gung University (Taiwan) and Director of the Reliability Science and Technology Center. Since 2024, he has also held the presidency of the Taiwan Reliability Technology Promotion Association. His career began in 1984 at Fairchild Semiconductor, followed by pivotal roles at Hewlett-Packard and Chartered Semiconductor, which built his cross-disciplinary expertise in materials, devices, and system-level reliability before he transitioned to academia in 1996.

Professor Tan is a Senior Member of IEEE and a Fellow of several prestigious institutions, including the Singapore Quality Institute, Institute of Engineers, Singapore and the International Association of Advanced Materials, Swedan. He is a contributor to international standards like IEEE 1624 and IEEE 1413. Since 2007, he has served as an IEEE EDS Distinguished Lecturer, delivering over 40 keynote addresses and providing systematic reliability training at major conferences such as IRPS, RAMS, and EDTM.

He has Published over 400 papers in high-impact journals and authored 14 books on reliability, with his work on Simulated Annealing exceeding 60,000 downloads.  He is recognized among Stanford University’s Top 2% Scientists worldwide, specifically ranking in the top 0.043% for Semiconductor Reliability.  He also provided expert consulting to more than 50 international organizations, including NASA, TSMC, Microsoft, the Taiwan Space Agency, and Aptiv.

Speech Title: A Multi-Physics Toolkit for Predictive Electromigration Modeling in Advanced IC Interconnections

Abstract: As semiconductor technologies advance toward complex chiplet integration and extreme miniaturization, the reliability of integrated circuit (IC) interconnections has emerged as a primary bottleneck for system performance. High current densities in these scaled interconnects make electromigration (EM) a critical failure mechanism. However, traditional assessment methods, such as Black’s Equation, are increasingly inadequate; they lack the capability to localize void-nucleation sites or effectively couple the complex 3D multi-physics driving forces—specifically thermal and thermo-mechanical stress gradients—present in realistic structures.

This talk introduces an advanced simulation toolkit developed as an Ansys Customization Toolkit designed for the rapid and accurate assessment of interconnect reliability. By utilizing a dynamic Atomic Flux Divergence (AFD) formulation derived from the first principles of thermodynamics, the toolkit captures the spatial-temporal evolution of EM-induced degradation.

A key innovation of this toolkit is its integration of microscale defect dynamics and energy barriers—parameters often experimentally inaccessible—computed via Density-Functional Theory (DFT) and Finite-Element Analysis (FEA). This enables the modeling of synergistic effects between electron-wind, thermal gradients, and stress-migration in a full 3D environment.  With such ab-initio modeling, strong correlation between estimated failure times and experimental data, achieving low error rates for Copper (0.37%) and Aluminum (0.27%) interconnects are observed.  This toolkit can facilitate the evaluation of novel materials, barrier metals, and layouts before committing to resource-intensive back-end-of-line (BEOL) process development.

By providing a robust predictive framework, this toolkit serves as a vital tool for optimizing reliability and accelerating the development cycle of advanced integrated systems.

Mohammad SAMIZADEH NIKOO

Nanyang Technological University, Singapore

Mohammad Samizadeh Nikoo is a Nanyang Assistant Professor in the School of Electrical and Electronic Engineering (EEE) at Nanyang Technological University (NTU), Singapore. He is the founding director of the Innovative Electronic & Electromagnetic Device Laboratory (i–Lab). He received his PhD from EPFL, Switzerland, in 2022. In the same year, he joined the Integrated Systems Laboratory at ETH Zurich as a research scientist, before beginning his tenure-track appointment at NTU in 2023. Dr. Samizadeh Nikoo is a Fellow of the National Research Foundation, Singapore (Class of 2024). He has received several distinctions and awards and currently serves as the lead principal investigator (PI) on multiple national research projects. His research focuses on developing a new generation of high-frequency semiconductor components for future information technologies. 

Speech Title: High-Performance Electronic Metadevices for Millimeter-Wave and Terahertz Integrated Circuits

Abstract: Approaching the terahertz band from the electronics side is of great technological importance, with the promise of advancing next-generation wireless communication systems toward 6G and beyond. However, inherent limitations of high-speed transistors, the primary building blocks of monolithically integrated high-frequency circuits, have hindered the realization of high-performance terahertz electronics. 

Electrical metastructures offer an alternative paradigm, in which modulation of the conductivity of a semiconducting layer controls collective quasi-electrostatic responses within a lumped structure, enabling electronic functionalities such as switching, mixing, and parametric amplification. Compared with conventional transistors, electrical metastructures enable ultra-low contact resistances, leading to record-high switching cutoff frequencies well beyond 10 THz in a compact device platform, referred to as electronic metadevices.

The first part of this talk highlights recent advances in III-nitride electronic metadevices operating up to 1 THz and introduces a new generation based on quasi-one-dimensional electrical metastructures with enhanced electrical performance. We present theoretical insights into the collective responses governing the operation of electronic metadevices and elucidate their ultimate performance limits. In the second part, we introduce a metastructure-based paradigm for directly realizing high-performance millimeter-wave and terahertz components with ultracompact footprints, demonstrated the compatibility of metatronic devices with commercial silicon processes. 

Eleni MAKARONA

Institute of Nanoscience and Nanotechnology, NCSR “Demokritos”, Greece

Dr. Eleni Makarona is Director of Research at the Institute of Nanoscience and Nanotechnology, NCSR "Demokritos", Greece. She holds a PhD in Physics from Brown University (USA), where she trained under Prof. Arto V. Nurmikko on III-nitride optoelectronics, supported by a competitive graduate fellowship awarded to the top 10% of international applicants.

Her research spans two parallel axes maintained continuously for nearly two decades: silicon photonic biosensors, and chemically synthesized metal oxide nanostructures. Her work on photonic sensors spans applications in biodiagnostics, food safety and quality assurance, and environmental monitoring. Moreover, she is co-inventor of the Broadband Mach-Zehnder Interferometer and Broadband Young Interferometer detection architectures — novel sensing principles that progressed from fundamental invention through patents to international prototype deployment. In metal oxide nanostructures, her work follows a material-first philosophy in which device concepts emerge from deep understanding of defect-driven mechanisms, spanning optoelectronics, sensing, energy harvesting, and hardware security.

She has led or coordinated competitive research programs across European and national frameworks, and has delivered invited presentations at international conferences. She was awarded the Greek L'Oréal–UNESCO Award For Young Women in Science in 2010.

Speech Title: Scalable Functional Devices Based on Chemically Synthesized ZnO Nanostructures: Bridging Synthesis and Device Functionality

Abstract: Low-cost, chemically synthesized metal oxide nanostructures offer a compelling pathway toward scalable, cost-efficient, and sustainable electronic and sensing devices. However, building functional devices from such nanostructures requires more than mastering fabrication and compatibility with standard micro/nanofabrication processes — it demands a deeper understanding of the underlying physical mechanisms governing the material itself and of how these translate into, and ultimately dictate, device performance.

This talk presents a device-oriented framework in which zinc oxide (ZnO) serves as a representative material platform. Central to this framework is the systematic investigation of defect-driven mechanisms emerging from the growth environment — mechanisms that, contrary to conventional device design assumptions, are shown to be the dominant determinants of functional behavior rather than structural geometry or intentional doping alone.

This perspective enables the development of functional systems across diverse application domains. Representative implementations span ZnO-based homojunction devices, sensing platforms exploiting defect-mediated mechanisms, energy harvesting systems, and hardware security elements. Collectively, these demonstrate a coherent, fabrication-compatible, and scalable pathway for functional device realization from chemically synthesized nanostructures — one that redefines material imperfection not as a limitation to be suppressed, but as a design parameter to be understood, controlled, and exploited. 

Qianqian Huang

Peking University, China

Prof. Qianqian Huang is a Full Professor with Tenure in the School of Integrated Circuits at Peking University. Her research interests are in the area of emerging low-power devices for diverse applications, in particular tunnel devices and ferroelectric devices. She has authored/co-authored more than 100 technical papers in international journals and conferences and held more than 70 granted patents. She is the recipient of Chang Jiang Scholar (2023), the Chinese Young Women in Science Award (2022), Xplorer Prize (2020), IEEE EDS Early Career Award (2019), etc.

Speech Title: Si Hybrid Tunnel FET-CMOS Foundry Platform for Ultra-low-Power Circuit Applications

Abstract: This work demonstrates the recent progress on 55 nm Tunnel FET(TFET)-CMOS hybrid integration platform and its ultra-low-power circuit applications. By integrating the bulk-Si-based novel dopant-segregated TFET (DS-TFET) with large ION and record high ION/IOFF ratio, as well as the novel laminated isolation technology into the CMOS baseline technology, energy-efficient TFET-CMOS hybrid circuits are experimentally realized. 1Kbit TFET-Gated-Ground SRAM is implemented and demonstrated in MCU always-on domain showing sub-100nA ultra-low leakage, and a 6T hybrid TFET-CMOS SRAM-based digital CIM accelerator is designed showing high energy efficiency without performance or area penalty. Moreover, a novel DS-TFET-like device (AsyFET) with ultralow off-state leakage current and bidirectional conductivity is further demonstrated as the write transistor of 2T0C eDRAM, leading to the long retention of 3.9 s in 55nm technology node. The TFET-CMOS hybrid platform of this work demonstrates the great potential for cutting-edge power-dieting applications.

Shurong Dong

Zhejiang University, China

Qiu Shi Distinguished Professor and director of Sensing and Micro-Integration Institute of Zhejiang University, Chief scientist of special project of the Ministry of Science and Technology, Military Strategic Expert Electronic field Committee, National Brain-Computer Interface Standards Committee, International PI of Cambridge University, One of the top 2% global scientists. He mainly engages in research on brain-machine interfaces and smart medical MEMS microsystem technologies. He has published 229 SCI papers, has an H-index of 48, and 6,809 citations on Google, 131 invention patents.

Speech Title: Multimodal Integrated Neural Electrode Based on Flexible Electronics

Abstract: Neural monitoring is a fundamental technology in neuroscience and neurological diseases. Multimodal neural monitoring can better observe neural and brain activity from multiple perspectives. How to integrate various observation techniques in a small area and meet the needs of different application scenarios is currently a challenge in the field of brain and neuroscience. This article introduces our team's recent work from implanted electrodes to wearable non-invasive electrodes, focusing on multimodal integrated neural electrode technology based on flexible electronics,  so as to provide a reference for scientific research.

Chao Ma

Xi’an Jiaotong University, China

Dr. Chao Ma is currently an Associate Professor and Ph.D. Supervisor at the School of Microelectronics, Xi’an Jiaotong University, and was selected for the XJTU Young Talent Support Plan. He received his Ph.D. degree in Electrical Engineering from Xi’an Jiaotong University in 2021, during which he was a visiting scholar at the University of California, Los Angeles (UCLA). After graduation, he conducted postdoctoral research at the School of Electronics, Peking University, as a “Boya” Postdoctoral Fellow. His research interests lie in high-performance pressure sensing and low-dimensional device integration, with a focus on: (1) AI-enabled tactile dexterous hands; (2) novel-principle sensing devices and electronic circuits, including (but not limited to) non-Hermitian electronic circuits; and (3) low-dimensional device integration for in-sensor computing. In recent years, he has published papers in leading journals, including Nature Electronics (front cover), Nature Communications, ACS Nano, and IEEE Electron Device Letters. He also holds five granted Chinese invention patents.

Speech Title: Contact-dominated, field-enhanced flexible pressure sensors toward high-performance robotic skin

Abstract: Motivated by the vision of functionalizing diverse human orientated future intelligent technologies with the ability to accurately and robustly detect various mechanical stimuli and interactions, intense efforts have been devoted to designing high-performance flexible pressure sensors, in particular for typical capacitive ones that feature low power consumption to support long-term continuous detection/monitoring. However, capacitive pressure sensors essentially suffer from limitations in terms of sensitivity, linearity, and working range. Here, we report a design strategy based on contact-dominated localized electric-displacement-field-enhanced capacitance and contact mechanics to dramatically improve the sensing response and linearity of capacitive sensors over a broad pressure range. We present a novel construction of integrated sensors by employing our contact-dominated design with floating-gate low-dimensional semiconductor transistors that enables the sensor to fully exploit the transistor’s on/off ratio range with enhanced sensing performance at a low operating voltage. Moreover, our sensor-equipped robotic arm demonstrates the potential to evaluate physical properties of fluids, and precisely and dynamically control to handle manipulation tasks. The proposed strategy can provide general design guidance for high-performance capacitive sensor, which would have a significant impact on human orientated future intelligent technologies.

Hong Kong University of Science and Technology (Guangzhou), China

Prof. Jiang Xu received his PhD from Princeton University and worked at Bell Labs, NEC Labs, and a startup company which is acquired by Qualcomm. He is the Founding Head of Microelectronics Thrust at Hong Kong University of Science and Technology (Guangzhou). Prof. Xu serves as the Associate Editor for IEEE TCAD and on the steering committees, organizing committees, and technical program committees of many international conferences, including OFC, DAC, DATE, ICCAD, CASES, CODES+ISSS, ASP-DAC, etc. Prof. Xu is awarded IEEE Computer Society Distinguished Contributor as the Charter Member in 2021. He was an IEEE Computer Society Distinguished Visitor and an ACM Distinguished Speaker. He authored and coauthored more than 180 book chapters and papers in peer-reviewed international journals and conferences. Prof. Xu and his students received Special Feature Award from ASP-DAC in 2026, Best Paper Award from the International Symposium on Memory Systems in 2023, IEEE Technical Committee on VLSI Best Paper Award of ISVLSI in 2018, and Best Poster Award from AMD Technical Forum and Exhibition in 2010. His research areas include AI system, electronic-photonic integration, power delivery and management, and hardware/software codesign.

Speech Title: Breaking Interconnect Wall with Electronic-Photonic Integration

Abstract: In the last 15 years, AI applications have required 4.3X more computation capacity every year, while Moore's Law can only offer 1.7X per year. AI systems are relying on not only advanced integration but also aggregation of growing numbers of GPU, CPU, accelerators and memories to meet the burgeoning performance requirements of AI applications under tight cost, energy, thermal, space, and weight constraints. However, interconnect technology develops slower than GPU, CPU and accelerators, and the gap is widening at 1.47X per year. This interconnect wall has become the major bottleneck of AI systems. Electronic-photonic integration piggybacks onto matured fabrication technologies to provide viable solutions to break the interconnect wall. Based on our decade-long quest to transform existing electronic computing systems with photonics, this talk will highlight our recent progress on electronic-photonic integration for aggregated systems.

Southern University of Science and Technology, China

Quan Pan (Senior Member, IEEE) received his B.S degree in Electrical Engineering (EE) at University of Science and Technology of China (USTC) in 2005, and his Ph.D. degree in Electronics and Computer Engineering (ECE) at the Hong Kong University of Science and Technology (HKUST) in 2014. 

From 2014 to 2018, he was Senior Staff Engineer in one Silicon Valley startup company, working on 400GbE high-speed SerDes. He joined in the School of Microelectronics, Southern University of Science and Technology as an assistant professor in 2018 and now a tenured full professor. His research interests include High-speed optical transceiver, wireless and wireline circuit design. Dr. Pan has contributed more than 80 peer-reviewed articles. He received the 2017 Outstanding Young Author Award of IEEE Circuits and System Society. He serves as an active reviewer for many international journals, including JSSC, TCAS, TVLSI, JLT, PTL, JoS, and et al.

Speech Title: Low-Power Wireline Optical transceivers for Emerging High-Speed Communications

Abstract: Low-power wireline integrated circuits have become extremely attractive since they are extensively adopted in high-speed communications, such as local area networks, board-to-board, and data center-to-data centers. Energy-efficient 56-224Gbps/lane links with sophisticated equalizations and modulations are studied, including analog front-ends, high-speed drivers, and crosstalk cancellations among multi-channel systems. Moreover, high-speed optical communication ICs have been very charming in recent years, including transimpedance amplifiers, continuous-time linear equalizers, decision feedback equalizers, feedforward equalizers, MZM/VCSEL/DML drivers and clock data recovery circuits.

Yokohama National Univerisy, Japan

Dr. Mengnan Ke is an Associate Professor at the Institute for Multidisciplinary Sciences, Yokohama National University, Japan. He received his B.E. degree in Microelectronics from South China University of Technology in 2012 and his M.E. and Ph.D. degrees in Electrical Engineering from the University of Tokyo in 2015 and 2018, respectively. He previously worked as an Assistant Professor at Tokyo University of Science, Japan, from 2018 to 2021 and Chiba University, Japan, from 2021 to 2024. His research interests include new channel material MOSFETs, interface physics, and advanced transistor technologies. He has led multiple JST and JSPS research projects and has published several papers as the first author in IEDM and IEEE Transactions on Electron Devices.

Speech Title: Understanding Slow Trap Characteristics and Degradation in GeOx/Ge MOS Structures

Abstract: Ge, with higher electron and hole mobility than Si, has attracted increasing attention as a channel material for next-generation MOSFETs. However, a large number of slow traps at GeOx/Ge MOS interfaces leads to significant reliability degradation.To understand the physical origin of slow traps in Ge MOS interfaces, we systematically investigate electron and hole traps in GeOx, Al2O3, and other high-k dielectrics, including Y2O3, HfO2, and La2O3.We demonstrate that the high density of slow traps in Al2O3/GeOx/Ge MOS structures formed by plasma oxidation can be effectively suppressed by a newly developed ALD-based Y-doping technique.

Beijing Jiaotong University, China

Tao Deng is a Professor and PhD Supervisor at the School of Electronic and Information Engineering, Beijing Jiaotong University. He is a recipient of the National Young Talent Program, Deputy Dean of Tianyou Zhan College, and Director of the Institute of Micro and Nano Electronics. He has led more than 10 national-level research projects, including key basic research program of the National Science and Technology Commission, pre-research funds, and National Natural Science Foundation of China projects. He has published over 90 peer-reviewed papers in prestigious journals and conferences such as Nano-Micro Letters, Advanced Functional Materials, Nano Letters, and IEEE MEMS, and owns more than 10 authorized invention patents. He has received numerous awards including the Best Researcher Award in International Sensing Technology and the Best Paper Award at IEEE NANO. Several of his developed devices have been applied in industrial applications.

Speech Title: Self-Assembled 3D MEMS Sensors

Abstract: As Moore’s Law approaches its physical limit, the More‑than‑Moore strategy has become essential for advanced microelectronic devices. Graphene‑based photodetectors face low absorption efficiency, while conventional two‑dimensional (2D) structures restrict device performance. This talk introduces high‑performance sensors enabled by self‑assembled three‑dimensional (3D) MEMS microtube optical resonators. The 3D architecture strongly enhances light–matter interaction, boosting responsivity by three orders of magnitude over 2D devices, with terahertz response and polarization sensitivity. Heterojunction integration with SWCNTs, TiO2, and MoS2 further improves performance, enabling self‑powered UV detection, optoelectronic synaptic functions, and polarization imaging. Inspired by spider’s mechanoreceptors, a 3D cilia‑like omnidirectional vibration transducer was developed based on flexoelectricity, delivering ultrahigh sensitivity and broad bandwidth. Combined with a 1DCNN decoupling algorithm, directional recognition reaches 97.18%. This work validates the potential of self‑assembled 3D MEMS for high‑sensitivity sensing and future integrated applications.

Xidian University, China

Zhihong Liu is a full Professor at the School of Microelectronics and the Guangzhou Institute of Technology, Xidian Unviersity. He is a Senior Member of IEEE. He received his B.S. and M.S. degrees from Nankai University and the Institute of Semiconductors, Chinese Academy of Sciences, respectively, and his Ph.D. from Nanyang Technological University (NTU), Singapore. In 2007, he joined Temasek Lab (TL) at NTU as a Research Associate, where he worked on the R&D of GaN microwave devices and MMIC fabrication technologies. In 2011, he joined the Singapore-MIT Alliance for Research and Technology (SMART) as Postdoc Associate, later severing as Research Scientist and Principal Research Scientist, focusing on GaN microwave/mm-wave/THz devices, GaN–Si CMOS heterogeneous integration technologies, and GaN power electronic devices. He joined Xidian University, China as a full Professor in 2019. From 2020-2025, he served as the founder and Executive Director of the Guangzhou Wide-Bandgap Semiconductor Innovation Center (GWSIC) at Xidian University. His current research interests include wide-bandgap and ultra-wide-bandgap semiconductor electronic devices and integrated circuits, with a particular focus on advanced GaN-based technologies.

Speech Title: Progress of GaN-on-Si RF Devices

Abstract: As a wide-bandgap semiconductor, GaN offers broad application prospects in RF fields such as radar, satellite, and 5G/6G communications. Benefiting from the advantages of GaN-based semiconductors, including a high critical electric field, high 2DEG concentration, high electron mobility, and high saturation velocity, GaN electronic devices and integrated circuits (ICs) possess excellent characteristics such as high output power, high efficiency, high-temperature operation ability etc. GaN grown a Si substrate, so called GaN-on-Si, combines the performance of GaN and the advantages of Si substrates, offering low cost, large-wafer availability, and the potential for mass production. In this talk, we will provide an overview of our recent research progress in GaN-on-Si RF devices and MMICs. Key topics include fabrication technology for 6-inch wafer C-to-Ka band GaN-on-Si device and MMICs, GaN mm-wave and THz power and low-noise transistors, and low-voltage GaN-on-Si RF devices for mobile terminal applications.

Zhejiang University, China

Dr. Cheng Zhuo is a Qiushi Distinguished Professor at Zhejiang University and Vice Dean of the College of Integrated Circuits. His research interests include VLSI design, electronic design automation (EDA), and AI algorithms and systems. He has published over 200 papers in leading conferences and journals in these areas, earning five Best Paper Awards and seven Best Paper Award nominations. He currently serves or has previously served as an associate editor for journals including IEEE TCAD, ACM TODEAS, and Elsevier Integration, and has served as Chair of the ACM SIGDA East China Chapter. He has also received the First Prize of the Zhejiang Provincial Science and Technology Progress Award and the First Prize of the Zhejiang Provincial Teaching Achievement Award, among other honors.

Speech Title: AI-Driven Virtual Fabrication for ICs

Abstract: Amid steadily increasing process complexity and rapidly rising R&D costs, IC fabrication faces major challenges, including long development cycles and costly trial-and-error. Traditional methodologies and infrastructure struggle to support rapid iteration and fast-paced innovation. AI-driven virtual fabrication is emerging as a promising pathway to accelerate IC R&D and enhance process optimization. This report outlines key research challenges and highlights practical efforts in virtual fabrication for ICs.

University of Science and Technology of China, China

Dr. Yuanyuan Shi currently works at University of Science and Technology of China (USTC) as a professor in the school of Integrated Circuits. Before joining in USTC, she was a senior researcher at IMEC, Belgium. She received her Ph.D. degree (with Excellent “Cum Laude” Honor and Extraordinary PhD prize) from University of Barcelona in 2018. Her research interests focus on 2D and oxide semiconductors based thin-film transistors for logic, memory and brain-inspired computing. Dr. Shi has published more than 70 research articles (including Nature Electronics, IEDM, VLSI, ACS Nano, etc.), two book chapters and five international patents, etc. She served as a committee member for IEEE EDS Nanotechnology committee and several IEEE flagship conferences, including IRPS, EDTM and IPFA. Dr. Shi also serves as an active reviewer for Nature, Nature Electronics, Nature Materials, Nature Communication, ACS Nano, IEEE Electron Device Letters, and others. Dr. Shi is a recipient of Marie Skłodowska-Curie Individual Fellowship (European Commission), IEEE EDS PhD student fellowship (three winners globally each year), ADF-The Rising Stars Women in Engineering, Forbes 30 under 30 (Forbes), Park AFM award (Park Systems), etc.

Speech Title: 2D-semiconductor transistors for advanced logic and memory devices: from channel deposition to device integration

Abstract: Abundant-data computing such as big-data analytics, artificial intelligence (AI) and Internet of Things (IoT) demand extreme energy efficiency and concomitant improvement of cost performance of the electronic systems. Field-effect transistors (FETs) represent the fundamental building blocks for modern computer processors. The number of transistors in a typical microprocessor has followed a remarkable exponential growth since the 1960s, a trend known as Moore’s law. By making the device smaller, more transistors can be packed into a single chip with much improved performance and reduced cost. The continued miniaturization of silicon microelectronics has fuelled the exponential growth of the integrated circuits for over half a century. Today, as silicon transistors enter the sub-10nm technology node with increasing technical challenges, the exploration of alternative device geometries or new channel materials is ever more important for future processor chip. Atomically thin two-dimensional (2D) semiconductors have attracted tremendous interest as a new channel material that could facilitate continued transistor scaling. To benefit from continuous scaling, the performance of the scaled 2D transistors needs to outperform Si technology nowadays. However, significant efforts are still required for channel material deposition, gate stack development and CMOS integration, etc. This talk will present our recent progress on 2D semiconductors based logic and memory devices, including selective-area deposition of high-quality channel, scaled-device integration and 2T0C DRAM application etc.  

Ye Lu

Fudan University, China

Dr. Ye Lu obtained his Ph.D. from the University of Pennsylvania in 2011, and he had been with Intel and Qualcomm from 2011-2019.  Dr. Lu joined Fudan University as a faculty member in early 2020, and his current research interest includes device and design co-optimization (DTCO) and AI-EDA. Dr. Lu is also a co-founder of RFIC-GPT. 

Speech Title: AI-Empowered Device Compact Model Creation 

Abstract: Device Compact Model (DCM) is a key bridge between device / process technology and circuit design simulations. Traditionally, DCM is created by physics-based formulas with human extracted parameters, however, this method is labor intensive and time consuming. This talk will cover our recent advancements in creating DCM using AI techniques such as neural networks and symbolic regression. In addition, the methodology of extracting DCM parameters using reinforcement learning (RL) will also be discussed. These results are expected to promote the efficiency as well as accuracy of future DCM development, and facilitate rapid DTCO cycles. 

Chunlei Wu

Fudan University, China

Prof. Chunlei Wu is an Associate Professor with the School of Microelectronics, Fudan University. Her research interests include in the area of post-Moore emerging logic devices, focusing on advanced Gate-All-Around FET, Complementary FET, etc. She has authored/co-authored more than 60 technical papers in international journals and conferences, held 16 granted patents. 

Speech Title: Physical Modeling of the Subthreshold Swing Saturation Behavior in Cryogenic MOSFETs

Abstract: Accurate device modeling is crucial to cryogenic CMOS technology development for future quantum computing applications. The existing band tail-based models, however, arbitrarily assume an unchanged band tail states distribution at deep cryogenic temperature, resulting in significant modeling error of the subthreshold swing (SS) saturation behavior in cryogenic MOSFET. In this work, a novel band tail model featuring a temperature-dependent band tail states distribution has been presented and verified. The introduction of temperature sensitive distribution of tail states enables accurate modeling of the SS saturation value and the critical temperature corresponding to SS deviation. The results provide a deeper insight into the physical mechanisms study and modeling of cryogenic MOSFETs.